1. Field of the Invention
The present invention relates to method and apparatus for detecting a position of a substrate by detecting a mark put on the substrate, and more particularly to method and apparatus suitable for detecting a position of a semiconductor wafer on an exposure apparatus for manufacturing a semiconductor device, laser repair apparatus or test apparatus.
2. Description of the Prior Art
Microminiturization of a large scale integrated circuit (LSI) pattern has been advancing year by year, and various projection type exposure apparatus which transfer a pattern on a mask (or reticle) onto a semiconductor wafer with unity magnification or at a reduced scale, have been used as circuit pattern print apparatus which meet requirements on microminiturization and which have a high productivity.
In the manufacture of the LSI, several or more pattern layers are sequentially formed on the wafer. If an alignment error (positional error) between the layers is not within a predetermined range, an intended conduction or insulation condition between the layers is not attained and the LSI does not perform its intended function. For example, for a circuit having a minimum line width of 1 .mu.m, only a positional error of 0.2 .mu.m at most is permitted. Accordingly, in the projection type exposure apparatus, various high precision alignment methods have been proposed to align a projection image of a pattern on the mask (or reticle) to a pattern (chip) formed on the wafer.
Most of those alignment methods optically detect an alignment key mark formed on the wafer. Accordingly, in many cases, the alignment precision depends on the alignment mark on the wafer. The affect of the wafer process to the alignment mark is larger in later step of the process, and the geometry of the mark is more degraded in the later step. This means that a photo-electric signal detected from the mark includes a distortion due to the geometry degradation together with a high optical reflection factor on a surface of a metalized (Al) wiring layer in the latter step of the process of the optical alignment. As a result, the precision of position detection of the mark is lowered and the alignment precision is lowered. Since a higher alignment precision is required as the wafer process proceeds, the alignment is not done in a good condition because of the lower precision due to the degradation of the mark geometry, and a yield of the chip is reduced.